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CMOS Static RAM 64K (8K x 8-Bit)
Features
High-speed address/chip select access time - Military: 20/25/35/45/55/70/85/100ns (max.) - Industrial: 25/35ns (max.) - Commercial: 15/20/25/35ns (max.) Low power consumption Battery backup operation - 2V data retention voltage (L Version only) Produced with advanced CMOS high-performance technology Inputs and outputs directly TTL-compatible Three-state outputs Available in 28-pin DIP, CERDIP and SOJ Military product compliant to MIL-STD-883, Class B
IDT7164S IDT7164L
x
Description
The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Address access times as fast as 15ns are available and the circuit offers a reduced power standby mode. When CS1 goes HIGH or CS2 goes LOW, the circuit will automatically go to, and remain in, a lowpower stand by mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28pin 600 mil CERDIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
x x
x
x x x x
Functional Block Diagram
A0 VCC ADDRESS DECODER 65,536 BIT MEMORY ARRAY GND
A 12
0
7
I/O 0 I/O CONTROL
I/O7
CS1 CS2 OE WE
CONTROL LOGIC
2967 drw 01
DECEMBER 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-2967/11
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Pin Configurations
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Absolute Maximum Ratings(1)
VCC WE CS2 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
,
Symbol VTERM
(2)
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Com'l. -0.5 to +7.0
Mil. -0.5 to +7.0
Unit V
D28-1 D28-3 P28-1 P28-2 SO28-5
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 1.0 50
-55 to +125 -65 to +135 -65 to +150 1.0 50
o
C C C
o
o
W mA
2967 tbl 02
DIP/SOJ Top View
2967 drw 02
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
Pin Descriptions
Name A0 - A12 I/O0 - I/O7 CS1 CS2 WE OE GND VCC Description Address Data Input/Output Chip Select Chip Select Write Enable Output Enable Ground Power
2967 tbl 01
Truth Table(1,2,3)
WE X X X X H H L CS1 H X VHC X L L L CS2 X L VHC or VLC VLC H H H OE X X X X H L X I/O High-Z High-Z High-Z High-Z High-Z DATAOUT DATAIN Function Deselected - Standby (ISB) Deselected - Standby (ISB) Deselected - Standby (ISB1) Deselected - Standby (ISB1) Output Disabled Read Data Write Data
2967 tbl 03
NOTES: 1. CS2 will power-down CS1, but CS1 will not power-down CS2. 2. H = VIH, L = VIL, X = don't care. 3. VLC = 0.2V, VHC = VCC - 0.2V
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input HIGH Voltage Input LOW Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 VCC + 0.5 0.8
Unit V V
Recommended Operating Temperature and Supply Voltage
Grade Military Temperature -55 C to +125 C -40 C to +85 C 0OC to +70OC
O O O O
GND 0V 0V 0V
Vcc 5V 10% 5V 10% 5V 10%
2967 tbl 04
V Industrial V
2967 tbl 05
____
Commercial
NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
2
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Capacitance (TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 8 Unit pF pF
2967 tbl 06
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
DC Electrical Characteristics(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S15 7164L15 7164S20 7164L20 Com'l. 100 90 170 150 20 3 15 0.2 Mil. 110 100 180 160 20 5 20 1 Com'l. 90 80 170 150 20 3 15 0.2 7164S25 7164L25 Ind. 90 80 170 150 20 3 15 0.2 Mil. 110 100 180 160 20 5 20 1
2967 tbl 07
Symbol ICC1
Parameter Operating Power Supply Current CS1 = VIL, CS2 = VIH, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current CS1 = VIL, CS2 = VIH, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level), CS1 > VIH, CS2 < VIL, Outputs Open, VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level), f = 0 (2), VCC = Max. 1. CS1 > VHC and CS2 > VHC, or 2. CS2 < VLC
Power S L S L S L S L
Com'l. 110 100 180 150 20 3 15 0.2
Unit mA
ICC2
mA
ISB
mA
ISB1
mA
7164S35 7164L35 Symbol ICC1 Parameter Operating Power Supply Current CS1 = VIL, CS2 = VIH, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current CS1 = VIL, CS2 = VIH, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level), CS1 > VIH, CS2 < VIL, Outputs Open, VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level), f = 0(2) , VCC = Max. 1. CS1 > VHC and CS2 > VHC, or 2. CS2 < VLC Power Com'l. S L S L S L S L 90 80 150 130 20 3 15 0.2 Ind. 90 80 150 130 20 3 15 0.2 Mil. 100 90 160 140 20 5 20 1
7164S45 7164L45 Mil. 100 90 160 130 20 5 20 1
7164S55 7164L55 Mil. 100 90 160 125 20 5 20 1
7164S70 7164L70 Mil. 100 90 160 120 20 5 20 1
7164S85/100 7164L85/100 Mil. 100 90 160 120 20 5 20 1
2967 tbl 08
Unit mA
ICC2
mA
ISB
mA
ISB1
mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
6.42 3
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DC Electrical Characteristics
Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage
(VCC = 5.0V 10%)
IDT7164S IDT7164L Min.
____ ____
Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS1 = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. MIL. COM'L. & IND MIL. COM'L. & IND
Min.
____ ____
Max. 10 5 10 5 0.4 0.5
____
Max. 5 2 5 2 0.4 0.5
____
Unit A A V
____ ____
____ ____
____
____
____
____
VOH
Output High Voltage
IOH = -4mA, VCC = Min.
2.4
2.4
V
2967 tbl 09
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ.(1) VCC @ Symbol VDR ICCDR tCDR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Input Leakage Current Test Condition
____
Max. VCC @ 3.0V
____
Min. 2.0
____ ____
2.0V
____
2.0V
____
3.0V
____
Unit V A ns
MIL. COM'L. & IND 1. CS1 > VHC CS2 > VHC, or 2. CS2 < VLC
10 10
____
15 15
____
200 60
____
300 90
____
0
tR(3)
tRC(2)
____
____
____
____
____
ns A
2967 tbl 10
IILII(3)
____
____
2
2
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested.
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2967 tbl 11
5V 480 DATAOUT 255 30pF*
, 2967 drw 03
5V 480 DATAOUT 255 5pF*
, 2967 drw 04
Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances
4
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V 10%, All Temperature Ranges)
7164S15(1) 7164L15(1) Symbol Parameter Min. Max. 7164S20(2) 7164L20(2) Min. Max. 7164S25 7164L25 Min. Max. 7164S35 7164L35 Min. Max. Unit
Read Cycle
tRC tAA tACS1(3) tACS2(3) tCLZ1,2(4) tOE tOLZ
(4)
Read Cycle Time Address Access Time Chip Select-1 Access Time Chip Select-2 Access Time Chip Select-1, 2 to Output in Low-Z Output Enable to Output Valid Output Enab le to Output in Low-Z Chip Select-1,2 to Output in High-Z Output Disab le to Output in High-Z Output Hold from Address Change Chip Sele ct to Power Up Time Chip Deselect to Power Down Time
15
____
____
20
____
____
25
____
____
35
____
____
ns ns ns ns ns ns ns ns ns ns ns ns
15 15 20
____
19 20 25
____
25 25 30
____
35 35 40
____
____
____
____
____
____
____
____
____
5
____
5
____
5
____
5
____
7
____
8
____
12
____
18
____
0
____
0
____
0
____
0
____
tCHZ1,2(4) tOHZ(4) tOH tPU(4) tPD(4)
8 7
____
9 8
____
13 10
____
15 15
____
____
____
____
____
5 0
____
5 0
____
5 0
____
5 0
____
____
____
____
____
15
20
25
35
Write Cycle
tWC tCW1,2 tAW tAS tWP tWR1 tWR2 tWHZ(4) tDW tDH1 tDH2 tOW
(4)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time (CS1, WE) Write Recovery Time (CS2) Write Enab le to Output in High-Z Data to Write Time Overlap Data Hold from Write Time (CS1, WE) Data Hold from Write Time (CS2) Output Active from End-of-Write
15 14 14 0 14 0 5
____
____ ____
20 15 15 0 15 0 5
____
____ ____
25 18 18 0 21 0 5
____
____ ____
35 25 25 0 25 0 5
____
____ ____
ns ns ns ns ns ns ns ns ns ns ns ns
2967 tbl 12
____
____
____
____
____ ____
____ ____
____ ____
____ ____
____
____
____
____
____
____
____
____
6
____ ____
8
____ ____
10
____ ____
14
____ ____
8 0 5 4
10 0 5 4
13 0 5 4
15 0 5 4
____
____
____
____
____
____
____
____
NOTES: 1. 0 to +70C temperature range only. 2. 0 to +70C and -55C to +125C temperature ranges only. 3. Both chip selects must be active for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested.
6.42 5
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (con't.) (VCC = 5.0V 10%, Military Temperature Ranges)
7164S45 7164L45 Symbol Parameter Min. Max. 7164S55 7164L55 Min. Max. 7164S70 7164L70 Min. Max. 7164S85/100 7164L85/100 Min. Max. Unit
Read Cycle
tRC tAA tACS1(1) tACS2(1) tCLZ1,2(2) tOE tOLZ(2) tCHZ1,2(2) tOHZ(2) tOH tPU(2) tPD(2) Read Cycle Time Address Access Time Chip Select-1 Access Time Chip Select-2 Access Time Chip Select-1, 2 to Output in Low-Z Output Enable to Output Valid Output Enab le to Output in Low-Z Chip Select-1,2 to Output in High-Z Output Disab le to Output in High-Z Output Hold from Address Change Chip Sele ct to Power Up Time Chip Deselect to Power Down Time 45
____ ____
55
____
____
70
____
____
85/100
____
____
ns ns ns ns ns ns ns ns ns ns ns ns
45 45 45
____
55 55 55
____
70 70 70
____
85/100 85/100 85/100
____
____
____
____
____
____
____
____
____
5
____
5
____
5
____
5
____
25
____
30
____
35
____
40
____
0
____
0
____
0
____
0
____
20 20
____
25 25
____
30 30
____
35 35
____
____
____
____
____
5 0
____
5 0
____
5 0
____
5 0
____
____
____
____
____
45
55
70
85/100
Write Cycle
tWC tCW1,2 tAW tAS tWP tWR1 tWR2 tWHZ(2) tDW tDH1 tDH2 tOW(2) Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time (CS1, WE) Write Recovery Time (CS2) Write Enab le to Output in High-Z Data to Write Time Overlap Data Hold from Write Time (CS1, WE) Data Hold from Write Time (CS2) Output Active from End-of-Write 45 33 33 0 25 0 5
____ ____ ____
55 50 50 0 50 0 5
____
____ ____
70 60 60 0 60 0 5
____
____ ____
85/100 75 75 0 75 0 5
____
____ ____
ns ns ns ns ns ns ns ns ns ns ns ns
2967 tbl 13
____
____
____
____
____ ____
____ ____
____ ____
____ ____
____
____
____
____
____
____
____
____
18
____
25
____
30
____
35
____
20 0 5 4
25 0 5 4
30 0 5 4
35 0 5 4
____ ____
____ ____
____ ____
____ ____
____
____
____
____
NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested.
6
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE tOLZ (5) CS2 tACS2 tCLZ2 (5) CS1 tACS1 tCLZ1(5) DATAOUT DATA VALID
2967 drw 05
tOH
tCHZ2 (5)
tOHZ (5) tCHZ1 (5)
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT DATA VALID
2967 drw 06
tOH
Timing Waveform of Read Cycle No. 3(1,3,4)
CS1
CS2 tACS2 tCLZ2 (5) tACS1 tCLZ1 (5) DATAOUT POWER SUPPLY CURRENT ICC ISB tPD
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
2967 drw 07
tCHZ2 tCHZ1 DATA VALID
(5) (5)
tPU
6.42 7
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5)
tWC ADDRESS
CS2 CS1 tAW tAS WE
(3)
tWR1(2)
tWP (5)
tOW(6)
DATAOUT tWHZ (6) DATAIN tDW DATA VALID
2967 drw 08
tDH1,2
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1)
tWC ADDRESS tAS CS2 tCW CS1
(4)
tWR2(2)
tWR1(2)
tAW WE tDW DATAIN tDH1,2
DATA VALID
2967 drw 09
NOTES: 1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2. 2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified tWP. 6. Transition is measured 200mV from steady state.
8
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low VCC Data Retention Waveform
DATA RETENTION MODE VCC tCDR CS VIH 4.5V VDR 2V VIH
2967 drw 10
4.5V tR
VDR
Ordering Information Commercial
IDT 7164 Device Type X Power XX Speed XXX Package X Process/ Temperature Range
Blank
Commercial (0C to +70C)
Y* P** TP*
300 mil SOJ (SO28-5) 600 mil Plastic DIP (P28-1) 300 mil Plastic DIP (P28-2)
15 20 25 35
Speed in nanoseconds
S L
Standard Power Low Power
* Available for 15ns and 20ns speed grades only. ** Available for 25ns and 35ns speed grades only.
2967 drw 11
6.42 9
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Ordering Information Industrial
IDT 7164 Device Type X Power XX Speed XXX Package X Process/ Temperature Range
I
Industrial (-40C to +85C)
P Y
600 mil Plastic DIP (P28-1) 300 mil Plastic SOJ (PJ28)
25 35
Speed in nanoseconds
S L
Standard Power Low Power
2967 drw 12
Ordering Information Military
IDT 7164 Device Type X Power XX Speed XXX Package X Process/ Temperature Range
B
Military (-55C to +125C) Compliant with MIL-STD-883, Class B
D TD
600 mil CERDIP (D28-1) 300 mil CERDIP (D28-3)
20* 25 35 45 55 70 85 100**
Speed in nanoseconds
S L
Standard Power Low Power
*
Available only in 600mil CERDIP (D28-1) and 300mil CERDIP (D28-1) and 300mil CERDIP (D28-3) packaging for a low power. ** Available only in 600 mil CERDIP (D28-1) packaging.
2967 drw 13
10
IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Datasheet Document History
1/13/2000 Pp. 1, 2, 3, 5, 10 Pp. 1, 3, 9 Pp. 1, 3, 6, 10 Pg. 3 Pp. 5, 6 Pg. 8 Pp. 9, 10 Pg. 11 08/09/00 02/01/01 12/07/01 Updated to new format Added Industrial Temperature range offerings Removed commercial 70ns speed grade offering Added 100ns speed grade specification details Revised notes and footnotes in DC Electrical tables Revised notes and footnotes in AC Electrical tables Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes Separated Ordering Information into commercial, industrial, and military offerings Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Add PJ28 to Industrial temperature.
Pg. 10
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax:408-492-8674 www.idt.com
for Tech Support: sramhelp@idt.com 800 544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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